It is known that as the dimensions of field effect transistors are scaled down for faster switching speed and lower current requirements, there arises the short channel effect. In order to increase the speed, the length of the channel between the source and drain of a field effect transistor is shortened. As this channel is shortened, there is a tendency in operation for breakdown to occur between the source and drain at voltages less than would otherwise be expected. This short channel effect is generally blamed on the spread, during operation, of depletion regions of the source and drain into the channel. As the depletion regions meet or as one extends from the drain/source to the source/drain, breakdown occurs.
Various techniques have been tried to attenuate this effect. One technique, described as the halo junction technique, involves forming highly doped regions of the same conductivity type as the semiconductor body, but of higher conductivity, around portions of the drain and source, excluding portions of the drain and source near the surface of the semiconductor body where the channel is formed when the transistor is biased on. This results in large steep p-n junctions that undesirably increases junction capacitance and leakage current.
Another technique uses a first blanket implantation of the semiconductor body area where a transistor is to be formed to form a buried region of the same conductivity type as the semiconductor body but of higher impurity concentration. This forms what is known as a retrograde type well. A second blanket implantation of the same conductivity type impurities is then done to modify the conductivity at and close to the surface of the semiconductor body so as to control threshold voltage. A gate dielectric layer is then formed followed by the formation of a gate. The gate is then used as a mask and there is an implantation of the source and drain, which are formed aligned to the gate. The resulting structure undesirably increases junction capacitance and leakage current.
Another known attempt to solve the short channel problem involves first implanting the surface of the chip where the inversion channel is to be formed to increase the doping at the surface, a step often practiced to control the threshold voltage of the device. This is followed by implanting the top surface more deeply to form a continuous layer extending the length of the active area that is of the same conductivity type as that of the source and drain and underlies the source and drain to limit the spread of the depletion regions.
However in such a device there is also increased undesirably the junction capacitance and the leakage current.
The present invention seeks to improve on both these techniques.